This year, the CAS (Malaysia) committee started the first series of awards in order to encourage students participation and excellence in Circuits & Systems related research and projects.

For PhD research, one award was conferred to Dr Wong Ming Ming for her research titled “VLSI Implementation and Its Optimisation for Digital Cryptosystems”. The abstract below summarizes her research work.

The complete thesis is available from Swinburne University’s digital repository.

Dr Wong Ming Ming receiving the award from CAS Vice Chair, Dr Asral Bahari Jambek during the CAS(M) Hi-Tea on 29th June 2013.
Dr Wong Ming Ming receiving the award from CAS Vice Chair, Dr Asral Bahari Jambek during the CAS(M) Hi-Tea on 29th June 2013.


The advent of the modern computing and the widespread of digital communications
fuel the need for secure and reliable methods in information and communication technologies.
Professional bodies around the globe have therefore emerged with a common
goal, that is to provide the highest level of information security in data communication
protocols and standards. Information security requires the use of cryptography
to provide authentication, confidentiality, integrity and non-repudiation as a means to
protect information from unauthorised access or accidental disclosure. Subsequently,
it is essential to ensure the effectiveness and efficiency of the selected cryptographic

In this doctoral work, two cryptographic schemes are investigated, which are namely
the Advanced Encryption Standard (AES) and the elliptic curve cryptography (ECC).
Naturally, this PhD thesis is organised into two parts according to our works in AES
and ECC respectively. In Part I, we attempt to optimise the non-linear S-box defined
over Galois field of 28, GF(28). The S-box is the major bottleneck to achieving small
area, high throughput and lower power consumption in AES hardware implementation.
More specifically, we take advantage of isomorphism to map the operation from
GF(28) to GF(((22)2)2) using CFA.

After a sequence of algorithmic and architectural optimisations, we manage to derive
an optimal construction for the S-box. The optimality that we seek for is one with minimum
gate counts and the shortest critical path. Furthermore, in each composite field
construction, there exists eight possible isomorphic mappings. Therefore, we design
a new common subexpression elimination (CSE) algorithm to choose the isomorphic
mapping that results in the lowest implementation cost. In the final stage, we exploit;
one Algebraic Normal Form (ANF) compliant with a custom fine-grained pipelining
scheme to achieve performance speed up and power reduction in our CFA AES S-box.
In the second part of this thesis, we focus on the optimisation approaches for elliptic
curve (EC) hardware cryptosystem. Scalar multiplication, kP, the fundamental to all
of the EC based cryptographic schemes, requires multiplicative inversions in affine coordinate
system. Therefore, compact and efficient finite field multiplicative inverter
design has become more important than ever before. In this work, we present a new
composite field composite multiplicative inverter of the form GF(ql), with q = 2n.m
that is suitable for hardware realisation. Considering both the security aspect and the
hardware cost required, we choose the composite field GF(((22)2)41) for realising our
EC cryptosystem. We employ a Fermat’s Little Theorem (FLT)-based inversion algorithm,
the Itoh and Tsujii inversion (ITI) algorithm over optimal normal type II (ONB
II) basis in our multiplicative inverter. Without the use of look-up tables (LUTs), the
arithmetic in the subfield, GF(24) will be performed in its isomorphic composite field,
GF((22)2), which leads to combinatorial implementation.

To validate all the theoretical work presented in this thesis, we implement all our designs
on field programmable gate arrays (FPGA) devices using the Altera Designer
Suite. The experimental results are presented in each part along with in-depth discussions
on the results obtained.