Circuits and Systems Society Malaysia

IEEE

Invited Lecture – Design For Test in System on Chip

Invited Lecture – Design For Test in System on Chip

Date: 1 June 2012

Time: 10 am – 12 pm

Venue: Bilik Seminar, Level 2, Faculty of Engineering, Universiti Putra Malaysia.

Biography: VY Liew is a Soft IP Architect of Intel Corporation’s Penang Design Center (PDC). He joined Intel in 1993 as a component Design Engineer. His current focus is on PDC Soft IP Roadmap, DFX design and validation, and leading the ease of use effort for SoC. Prior to Soft IP architect role, VY worked as Intel Platform Component Hub (PCH) DFX Architect for the last 7 years; and developed effective DFX solutions to HVM and Debug. He led the team to establish effective Hotham solution for Lynxpoint chipset in Intel next generation Haswell platform. In addition, VY is a Lynxpoint IOSF-SB architect driving standardization into chipset. VY is also the chair on PDC’s Universities Curriculum Team involving master research sponsorship for local universities. VY obtained his BSc from Science University of Malaysia, and he is currently holding 5 patents.

Abstract: Slowly, over the last four decades, industry has gradually begun to give attention to Design for Testability during the chip development. During its first two decades since its introduction in 1950’s, Design for Testability remained largely an “outsider” discipline of digital design, accepted only by a relatively small group of industry experts, until the idea finally began to take hold in the mid 1980’s. This field is getting more and more attention when the number of transistors increases tremendously and started to outrange the number of tests that can be performed to ‘troubleshoot’ a design. Increase in the number of device processes in advanced MOSFET which decreases the reliability of the transistor also makes DFT a must-have feature in a design to enable excellent time-tomarket and test quality. In this talk, the background of DFT will be provided, followed by the concept of testing and testability. Evolution of the DFT from simple design to SoC will be emphasized and finally, future challenges in SoC DFT will be discussed.

Download poster (PDF)

Leave a Reply